INTRODUCTION
Counter is a term that derived from the verb count which is the action of finding the number of elements of a finite set of objects or the process of determining the number or amount of countable things like apples. The traditional way of counting consists of continually increasing a device by a unit for every element of the set. The devices which are used to facilitate counting are called counters.Usually counters are used to count natural numbers (initially 0) and it counts until it reaches maximum allowed digits then either the count value will be brought to 0 and this operation called RESET , or value will be stacked and can not be increased any more , this case called overflow .
In electronics, counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. Generally there are two types of counters, up counters which increase the stored value, down counters which decrease the stored value. Both type can be implemented in one; we call it up / down counter and it's the type used in this project.
The counter can be synchronous or asynchronous, the main difference between them is the stored value (or count) of synchronous counter change under control of a particular clock signal whereas in asynchronous counter it performs counting regardless to any clock signal.
In this project the counter will perform an operation once for every clock cycle, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0.
In earlier time in order to make a counter the use of register-type circuits such as the flip-flop or simple logic gates was needed, but with revolution of technology the field-programmable gate array (FPGA) made things easier and more efficient. The FPGA is an integrated circuit designed to be configured by the customer or designer after manufacturing, hence designer can reconfigure the programmable logic components.
To program or configure FPGA a hardware description language (HDL) must be used, the HDL is any language from a class of computer languages or/and programming languages for formal description of electronic circuits and more specifically, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.
Since Xilinx is one of the most popular suppliers for programmable logic devices, this project will make use of the Xilinx FPGA and its software tool Xilinx ISE to synthesize and analysis the project design. The hardware description language will be VDHL.
Software Requirements
Xilinx ISE 12.1 The Web Edition.
Hardware Requirements
Xilinx FPGA
Family: Spartan3
Device: XC3S200
Package: FT256
Speed Grade: -4
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| Figure1: Counter's Inputs and Output Bus |
The Inputs for the counter will be:
Clock: this pin (or port) will have the clock signal. It can have 1 or 0 where 1 means the clock signal is going from down (low state) to up (high state), 0 is vice versa.
Reset: an input pin which will determine when the counter will be reset. It can have 1 or 0 where 1 means do reset , 0 do not rest ( keep counting or load ) .
Clock_Enable: this pin will tell the answer of question "should we do count?" It can have 1 or 0 where 1 mean do count, 0 means do not count.
Load_Enable: this pin will determine there is load or no. it can have 1 or 0 where 1 means we have load, 0 means we do not.
Count_direction: since this counter is UP/DOWN counter we should know when it will count up and down. It can have 1 or 0, 1 means count up (increment) whereas 0 means count down (decrement).
Input: this pin will have the value that will be loaded to the counter, since then we have 8-bit counter, it have eight bits.
The output will be:
Output: this bus will carry the count value which will be counted in the counter. It has 8-bits.
The counter in this project will Count up, Count down, Load a value to the counter and Reset the counter. as most of the technique used in programmable gate array a temporary signal must be declared , this signal will work internally in the FPGA and its job is to hold a temporary value until a particular process(s) finish after that the value will be given to the output port .
A temporary signal is a signal which won't exist all the time it will be created only when it is called by a process that includes a requirement of the signal to complete execution. When execution is finished the signal will be destroyed.
For instance the load operation will perform according to such a scenario , when the clock_enable port will have TRUE value in its port in some process and the value of Load_Enable was TRUE as well , then the conditions for performing the load operation were satisfied and the loading begins ,in this case the value which will be loaded in the counter will be waiting in front of port Input hence the value of the port input will be given to the internal temporary signal Count and when the process is finished the temporary signal count will give the stored value to the output port and the load operation will be done .
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| Figure 2: Demonstration of load operation. |
Often the counters output are connected to a display drive to output specific results, these display drives can be programmed in the same manner ( FPGA work) with different codes.
The output of the display drive in most cases will be wired to external display device like LCD drive or a matrix of LED's.
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| Counter's Output Simulation |
SUMMARY
| Approach Type | Optimized |
| Programming Language | VHDL |
| Processor | Spartan 6 |
| Software Components/Libraries | N/A |
| Compiler/Linker | Xilinx ISE Webpack |
